1. Field of the Invention
This invention pertains to a bipolar transistor structure and to a method for forming a portion of the structure comprising a self-aligned, trench-isolated emitter. A single layer of conductive material forms both the emitter and base contacts in the structure, which has particularly shallow emitter and base junctions (about 0.15 micrometer or less). The structure of the self-aligned, trench-isolated emitter permits overall size reduction of the transistor, whereby junction area which leads to parasitic capacitance, and accompanying leakage across junctions are reduced. The emitter structure also enables construction of an intrinsic device (comprising the emitter, an intrinsic base underlaying the emitter and a collector underlaying the intrinsic base) having improved function, since the structure permits improved base conductivity without generating peripheral transistor effects. The bipolar transistor can be either N-P-N type or P-N-P type depending on the materials of fabrication, although high speed devices are typically of the N-P-N type.
2. Background of the Invention
Known bipolar transistor device structures suffer significant limitations in terms of the size of base-collector junction area and collector-substrate junction area, due to the need to provide proper isolation between emitter and base contact regions on the upper surface of the device. In addition, the alignment requirements for the emitter, which are typically limited by photoresist capability also result in increased emitter-base junction area. These larger than desired junction areas can introduce unwanted parasitic capacitance which limits the device or circuit performance.
In addition, known device structures typically exhibit overlap of intrinsic and extrinsic base areas, which results in peripheral transistor effects which create disadvantages in terms of device function.
Examples of bipolar transistor device structures known in the art include the following U.S. Patents.
U.S. Pat. No. 4,722,908 to Burton, dated Feb. 2, 1988, discloses a process for fabrication of a bipolar transistor with a polysilicon ribbon.
U.S. Pat. No. 4,674,173 to Hahn et al., dated Jun. 23, 1987 discloses a method for fabricating a bipolar transistor which uses a polysilicon extrinsic base structure which is formed in a trench having a differential oxidation insulating layer at the bottom of the trench.
U.S. Pat. No. 4,663,831 to Birrittella et al., dated May 12, 1987 describes a method of forming transistors with poly-sidewall contacts using deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers.
U.S. Pat. No. 4,392,149 to Horng et al., dated Jul. 5, 1983, describes a self-aligned process for providing a bipolar transistor structure.
U.S. Pat. No. 4,381,953 to Ho et al., dated May 3, 1983, describes a polysilicon-base self-aligned bipolar transistor process.
U.S. Pat. No. 4,333,227 to Horng et al., dated Jun. 8, 1982, describes a method for fabricating a self-aligned micrometer bipolar transistor device.
Although the parasitics problem is recognized in much of the above art, and an effort is made to minimize overall device dimensions, the reduced dimension structures can create peripheral transistor effects which are detrimental to device function, offsetting the advantages obtained by the reduction of parasitics.